Title :
A design method of systolic arrays under the constraint of the number of the processors
Author :
Horiike, Satoshi ; Nishida, Shogo ; Sakaguchi, Toshiaki
Author_Institution :
Mitsubishi Electric Electronic, Amagasaki, Japan
Abstract :
This paper proposes a systemtic method to design systolic arrays under the constraint of the number of the processors. Our basic approach is to partition the large systolic array into the smaller number of groups, whose number is coincident with the number of processors to be used. We give the mathematical method to make at most one processor execute computation in each group. Then, each group can be replaced by one processor to satisfy the constraint of the number of the processors.
Keywords :
Convolution; Costs; Design methodology; Fabrication; Hardware; Laboratories; Matrix decomposition; Partitioning algorithms; Systolic arrays; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
DOI :
10.1109/ICASSP.1987.1169584