Title :
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder
Author :
Yang, Hao-I ; Lin, Yi-Wei ; Hsia, Mao-Chih ; Lin, Geng-Cing ; Chang, Chi-Shin ; Chen, Yin-Nien ; Chuang, Ching-Te ; Hwang, Wei ; Jou, Shyh-Jye ; Lien, Nan-Chun ; Li, Hung-Yu ; Lee, Kuen-Di ; Shih, Wei-Chiang ; Wu, Ya-Ping ; Lee, Wen-Ta ; Hsu, Chih-Chiang
Author_Institution :
Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R. O. C.
Abstract :
This paper presents a 1.0Mb high-performance 0.6V VMIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.
Keywords :
Arrays; CMOS integrated circuits; Random access memory; Sensors; Timing; Transistors; Voltage control;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271624
