Title :
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
Author :
Jiang, Jie-Hong ; Jou, Jing-Yang ; Huang, Juinn-Dar ; Wei, Jung-Shian
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Field Programmable Gate Arrays (FPGAs) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDDs) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLBs) in FPGAs. The experimental results on a set of benchmarks show that our algorithm can produce much better results than those of the previous approach (Wen-Zen Shen et al., 1995)
Keywords :
decision tables; field programmable gate arrays; logic CAD; BDD based; Binary Decision Diagrams; FPGA; LUT architecture; Roth-Karp decomposition; configurable logic blocks; lambda set selection; Binary decision diagrams; Boolean functions; Circuits; Data structures; Design engineering; Field programmable gate arrays; Logic; Matrix decomposition; Prototypes; Table lookup;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600139