Title :
Design and characterisation of thick oxide parasitic transistor for MIMOS 0.8-μm CMOS technology development
Author :
Chye, Roy Kooh Jinn ; Ahmad, Mohd Rais ; Ting, Toh Hong ; Suparjo, Bambang Sunaryo ; Wagiran, Rahman
Author_Institution :
Semicond. Technol. Center, Kuala Lumpur, Malaysia
Abstract :
The concept, design and characterisation of thick oxide parasitic transistors is investigated in this paper. The outcome includes the design from concept of two classes of thick oxide parasitic transistors, which consist of four different test structures. Both classes were used to evaluate the possibility of parasitic FET occurrence. They are class 1 (poly/field oxide and metal 1/field oxide) and class 2 (metal 1/BPSG and metal 2/BPSG/USG). Class 1 designs involved the conventional isolation technology used in the development of MIMOS 0.8 μm CMOS technology while class 2 were designed to imitate the condition of metal routing in circuit design. The results of some n- and p-channel thick oxide parasitic transistors are presented in this paper. All field threshold voltages obtained for the test structures are above 12 V. CADENCE Virtuoso Layout editor is used to generate the test structure layouts. The results of this study complement other test structures for MIMOS 0.8 μm CMOS technology development
Keywords :
CMOS integrated circuits; circuit layout CAD; dielectric thin films; integrated circuit design; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; integrated circuit testing; isolation technology; network routing; 0.8 micron; 12 V; CADENCE Virtuoso Layout editor; CMOS technology development; MIMOS CMOS technology development; Si-SiO2; circuit design; field threshold voltages; isolation technology; metal 1/BPSG test structure; metal 1/field oxide test structure; metal 2/BPSG/USG test structure; metal routing; n-channel thick oxide parasitic transistors; p-channel thick oxide parasitic transistors; parasitic FET occurrence; poly/field oxide test structure; test structure layouts; test structures; thick oxide parasitic transistor characterisation; thick oxide parasitic transistor design; thick oxide parasitic transistors; CMOS technology; Capacitors; Circuit synthesis; Circuit testing; Diodes; FETs; Isolation technology; MIMO; Monitoring; Routing;
Conference_Titel :
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on
Conference_Location :
Bangi
Print_ISBN :
0-7803-4971-7
DOI :
10.1109/SMELEC.1998.781165
