Parallel - pipelined radix-22 FFT architecture for real valued signals

This paper presents a novel parallel-pipelined architecture for the computation of real valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the redundancy of some computations with respect to complex FFT along with low multiplicative complexity of the radix-2² architecture. Folding transformation is used to derive a novel parallel-pipelined architecture by exploiting the redundancy in the modified flow graph. The proposed parallel architecture requires log₄N - 1 complex multipliers and N - 1 complex delay elements.