Butterfly and Inverse Butterfly nets integration on Altera NIOS-II embedded processor

The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described in, and the Altera NIOS-II processor. The BMU, described in VHDL, has been integrated in the processor using the Custom Logic feature and implemented on an Altera-Stratix FPGA.