Effect of order on MCM implementations of FIR filters

Field Programmable Gate Arrays (FPGAs) are becoming a popular choice for digital filter implementation over DSP processors for reasons of higher sampling rates and more flexibility in design. Designing an efficient digital filter can be achieved using Multiple Constant Multiplication (MCM). MCM implements multiplication by constants through the use of shifts and adds/subtracts. Using MCM to design a filter circuit and selecting FPGAs for its implementation results in area savings and higher speed. This paper demonstrates how area is impacted through the use of MCM for FPGA implementation.