A VLSI implementation of the partial rank algorithm for adaptive signal processing

This paper presents a VLSI architecture for implementing the Partial-Rank Algorithm used in adaptive beamforming. The architecture depends on VLSI computational hardware for vector operations which are the main computations needed for the algorithm. The systolic-like architecture presented is as flexible as the algorithm itself in the sense that higher order algorithms can be implemented by adding identical hardware. The implementation is shown to be extendable from an LMS algorithm to a full matrix algorithm.