Title :
A message passing coprocessor for distributed memory multicomputers
Author :
Hsu, Jiun-Ming ; Banerjee, Prithviraj
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
The authors present the architecture, methodology and performance evaluation of a message-passing coprocessor (MPC) which can accelerate message communication in a distributed memory multicomputer (i.e. iPSC/2 hypercube). The MPC is a microprogrammable processor which offloads from the CPU the burden of communication and speeds up the software processing by directly executing message passing instructions in microcode. It supports process scheduling, message buffer management, and fast buffer copying. The most unique feature of the MPC is that it performs software caching for expected message destinations and buffers. The MPC works closely with a virtual channel router which is a smart routing controller and supports virtual channels and cached circuits. The software and hardware overhead of communication can be reduced significantly by these two processors. The performance is confirmed by trace-driven simulation
Keywords :
parallel architectures; parallel machines; performance evaluation; satellite computers; cached circuits; distributed memory multicomputers; expected message destinations; fast buffer copying; iPSC/2 hypercube; message buffer management; message passing coprocessor; message passing instructions; microprogrammable processor; performance evaluation; process scheduling; routing controller; software caching; trace-driven simulation; virtual channel router; virtual channels; Acceleration; Central Processing Unit; Communication system control; Computer architecture; Coprocessors; Hypercubes; Message passing; Processor scheduling; Routing; Software performance;
Conference_Titel :
Supercomputing '90., Proceedings of
Conference_Location :
New York, NY
Print_ISBN :
0-8186-2056-0
DOI :
10.1109/SUPERC.1990.130092