A split control store VLSI for 32 kbps ADPCM transcoding

This paper describes the architecture used in a 16 pin CMOS VLSI Digital Signal Processor which was designed by the authors to perform both ANSI and CCITT versions of the ADPCM standard. The part is designed to run from a 20 MHz clock source with an instruction cycle time of 100 ns. This design is a good example of the power of application specific DSP designs to reduce the cost of implementing stable algorithms.