DocumentCode :
3016132
Title :
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
Author :
McGregor, Robert L. ; Antonopoulos, Christos D. ; Nikolopoulos, Dimitrios S.
Author_Institution :
Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA
fYear :
2005
fDate :
04-08 April 2005
Abstract :
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of multithreaded applications. The use of hybrid multiprocessors presents schedulers with the problem of job pairing, i.e. deciding which specific jobs can share each processor with minimum performance penalty, by running on different execution contexts. Therefore, scheduling policies are expected to decide not only which job mix will execute simultaneously across the processors, but also which jobs can be combined within each processor. This paper addresses the problem by introducing new scheduling policies that use run-time performance information to identify the best mix of threads to run across processors and within each processor. Scheduling of threads across processors is driven by the memory bandwidth utilization of the threads, whereas scheduling of threads within processors is driven by one of three metrics: bus transaction rate per thread, stall cycle rate per thread, or outermost level cache miss rate per thread. We have implemented and experimentally evaluated these policies on a real multiprocessor server with Intel Hyperthreaded processors. The policy using bus transaction rate for thread pairing achieves an average 13.4% and a maximum 28.7% performance improvement over the Linux scheduler. The policy using stall cycle rate for thread pairing achieves an average 9.5% and a maximum 18.8% performance improvement. The average and maximum performance gains of the policy using cache miss rate for thread pairing are 7.2% and 23.6% respectively.
Keywords :
bandwidth allocation; cache storage; multi-threading; processor scheduling; shared memory systems; Intel Hyperthreaded processor; Linux scheduler; cache miss rate; hardware multithreading; high-end computing nodes; hybrid multiprocessor; memory bandwidth utilization; scheduling algorithm; shared-memory multiprocessing; Computer science; Counting circuits; Educational institutions; Hardware; Interference; Multithreading; Processor scheduling; Runtime; Scheduling algorithm; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
Print_ISBN :
0-7695-2312-9
Type :
conf
DOI :
10.1109/IPDPS.2005.390
Filename :
1419847
Link To Document :
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