DocumentCode
3016171
Title
Testing TAPed cores and wrapped cores with the same test access mechanism
Author
Benabdenbi, Mounir ; Maroufi, W. ; Marzouki, Meryem
Author_Institution
LIP6 Lab., Paris, France
fYear
2001
fDate
2001
Firstpage
150
Lastpage
155
Abstract
This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM´s architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port
Keywords
automatic test equipment; automatic testing; boundary scan testing; computer architecture; integrated circuit testing; system buses; Boundary Scan Test Access Port; CAS-BUS; SoC; System On a Chip testing; TAPed cores; dynamically reconfigurable architecture; scalable architecture; wrapped cores; Content addressable storage; Laboratories; Petroleum; Standards development; Switches; System testing; System-on-a-chip; Time to market; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location
Munich
ISSN
1530-1591
Print_ISBN
0-7695-0993-2
Type
conf
DOI
10.1109/DATE.2001.915016
Filename
915016
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