New SRAM Cell Design for Low Power and High Reliability Using 32nm Independent Gate FinFET Technology

This paper proposes new methods for SRAM cell design in FinFET technology. One of the most important features of FinFET is that the independent front and back gates can be biased differently to control the current and the device threshold voltage. By controlling the back gate voltage of a FinFET, a SRAM cell can be designed for low power consumption. This paper proposes a new 8T (8 transistors) SRAM structure that reduces dynamic power for the write operation and achieves a wider SNM (static noise margin). Using the new FinFET based 8T SRAM cell, dynamic power consumption is reduced by nearly 48% and the SNM is widened up to 56% compared to the conventional 6T SRAM at the expense of 2% leakage power and 3% write delay increase.