A signal processing cell architecture

A data flow general purpose digital signal processor has been previously developed [1] for real time applications of digital signal processing. The Data Flow Signal Processor (DFSP) is attached to a host computer, and is based on a binary tree structure. It employs two types of cells: processing and arithmetic cells, and utilizes residue number system [2] for arithmetic operations. The objective of this work is to develop architecture of the processing cell [3]. This processing cell is simulated on a VAX 11/785 computer system utilizing A Hardware Programming Language (AHPL) [4]. Simulation results shows that processing cell architecture is valid and DFSP is capable of high throughput rates. This paper describes structure and operation of the processing cell.