An audio clock regenerator with a wide dividing ratio for HDMI

This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.