A 1.2V 2-bit phase interpolator for 65nm CMOS

We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from t_rise: 48ps → 200ps using a ratio t_rise/t_delay of at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations across process corners using extracted parasitic capacitances but ignoring MOSFET mismatch effects. Power consumption was estimated at 30nW/MHz → 38nW/MHz across a range of process variation corners in these operating conditions. Monte Carlo simulations across process and MOSFET mismatch conditions show large variations in estimated accuracy. Monte Carlo trials show the PI achieves a worst case DNL error (mean±3σ) of 1.06 LSB using t_rise/t_delay ratio of 5.3 and 48ps rise time, and a worst case DNL error (mean ±2σ) of 0.49 LSB for t_rise/t_delay ratio of 4 and 84ps rise time.