Implementation of an area efficient data converter with increased effective number of bits

Data converters, ADCs and DACs, interface the real world of analog signals to the digital domain. They can be classified as `Nyquist rate converters´ and `Over sampled converters´. Former operates at a sampling rate of twice the input signal frequency. They do not make use of the advantages of exceptional high speeds achieved in the current VLSI technology. Also the limitations in matching accuracy of the analog circuits needed in this type, limits their accuracy to an effective number of bits (ENOB) of 12 to 14 bits for various implementations. Over sampling data converters uses sampling rate much higher than Nyquist rate, typically higher by a factor between 8 and 512 or higher. They can achieve over 20 ENOB resolution at reasonably high conversion speeds. The engine behind this over sampling converter is a delta-sigma modulator. The main advantage of delta sigma modulator is that they offer a very good separation of input signal from the quantisation noise due to the over sampling process and noise shaping. The Signal to noise ratio (SNR) for a Nyquist rate converter depends on the number of bits of the converter. In this type SNR can be increased by approximately 6dB per bit. In over sampling converters the SNR depends on the depth of oversampling also, which is specified as `Oversampling ratio´ (OSR). Theoretically, for each doubling in sampling rate SNR can be be improved by a factor of 3dB, which corresponds to a half bit increment in Nyquist rate converters. Thus without increasing chip area SNR is increased. In this paper a 10 bit delta sigma DAC is implemented and SNR was measured with various sinusoids at different over sampling ratios. To reduce the number of transistors in the implementation, Minimal energy dual bit adder (MEDB adder) is used.