Macromodeling CMOS circuits for event driven simulation

Using a piece-wise linear source for modeling the input transitions, the logic delays and output transition times are characterized and accurately macromodeled with errors typically less than 1%. Two different logic levels are used at the 70% and 30% points in the transitions to define the “logic events” to circumvent characterized negative delay times. Input capacitance characterization which includes the Miller effect is described. Comparisons of HSpice simulations versus the event simulations for example logic blocks typically result in differences of less than 10%