Title :
A parameterized VLSI video-rate histogram processor
Author :
Richards, Brian ; Sherstinsky, Alex ; Brodersen, Robert W.
Author_Institution :
U.C. Berkeley, Berkeley, CA, U.S.A.
Abstract :
A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to support 10 MHz sample rates. The architecture was then implemented using high-level CAD tools to automate the design. Finally, the fabricated processor was connected to a second chip which implements a programmable look-up table function, to demonstrate real-time histogram equalization of 10 MHz video data.
Keywords :
Design automation; Histograms; Image segmentation; Pipeline processing; Pixel; Process design; Read-write memory; Table lookup; Testing; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
DOI :
10.1109/ICASSP.1987.1169677
