Hierarchical mixed-level simulation of VHDL descriptions

Author

Karnik, T. ; Saab, D.G. ; Kang, S.M. ; Lee, Y.K. ; Kim, K.H.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

170

Lastpage

173

Abstract

We present a hierarchical multilevel VHDL simulator for large systems described at the transistor, gate and higher levels. We exploit the hierarchy and regularity in VHDL descriptions to reduce the memory requirements drastically. The simulation algorithm handles MOS digital designs with bidirectional signal flow. We have augmented VHDL descriptions with signal strengths and timing; and also proposed a method to extend VHDL to accept transistor-level descriptions. Simulation results are provided for sample VHDL circuits

Keywords

MOS logic circuits; circuit analysis computing; digital simulation; hardware description languages; integrated circuit design; logic CAD; MOS digital designs; VHDL descriptions; bidirectional signal flow; hierarchical mixed-level simulation; memory requirements; multilevel VHDL simulator; regularity; sample VHDL circuits; signal strengths; simulation algorithm; transistor-level descriptions; Algorithm design and analysis; Circuit simulation; Delay; Discrete event simulation; Integrated circuit interconnections; Logic circuits; MOS devices; MOSFETs; Signal design; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404583

Filename

404583