DocumentCode
3016973
Title
A 40 MFLOPS digital signal processor: The first supercomputer on a chip
Author
Simar, Ray, Jr. ; Leigh, Tony ; Koeppen, Peter ; Leach, Jerald ; Potts, Jim ; Blalock, Denise
Author_Institution
Texas Instruments Inc., Houston, Texas
Volume
12
fYear
1987
fDate
31868
Firstpage
535
Lastpage
538
Abstract
The TMS320C30 is Texas Instruments´ third generation member of a family of compatible Digital Signal Processors. With a computational rate of 40 MFLOPS (Million Floating-Point Operations per Second), the TMS320C30 far exceeds the performance of any programmable DSP available today. Total system peformance has been maximized through internal parallelism, more than twenty four thousand bytes of on-chip memory, single-cycle floating-point operations, and concurrent I/O. The total system cost is minimized with on-chip memory and on-chip peripherals such as timers and serial ports. Finally, the user´s system design-time is dramatically reduced with the availability of the floating-point operations, general purpose instructions and features, and quality development tools.
Keywords
Central Processing Unit; Costs; Digital signal processing; Digital signal processors; Floating-point arithmetic; Instruments; Registers; Signal generators; Supercomputers; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
Type
conf
DOI
10.1109/ICASSP.1987.1169689
Filename
1169689
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