Design for Testability: The Path to Deep Submicron

Design has never been simple, but at 130 nm and below, and definitely at 90 nm, it is becoming increasingly difficult. Process and lithography issues continue to drive our advance to new technology nodes. Due to the effects of scaling, defect mechanisms are no longer easily identified with single "stuck at" fault models but rather are demanding far more complex and challenging solutions. For example, shorts are now being extracted from the physical layout of a design, with special tests being created to detect them. But this is just the beginning; delay testing of all transition faults is now a new objective of design for testability (DFT). New demands are being made on design to not only create the correct function and help with testing but also to help yield ramp-up. The areas of design for manufacturing (DFM) and design for yield (DFY) are now also talking hold as new requirements for design. Manufacturing and test are beginning to develop an even stronger relationship due to the close interconnection between yield ramp-up and diagnostics, which are supported by DFT structures included in the design