Abstract :
The conference theme of ITC 2005 focuses on evolutionary as well as revolutionary trends in test technology. It states: "Recent advances in areas such as on-chip compression, low-cost test, and data analysis have burst onto the scene and are being rapidly and widely adopted". Indeed, test compression is one of the fastest adopted DFT methodologies. It had been researched for ten years before it was commercially introduced four years ago, and now it has become the mainstream DFT technology. Just a couple of years ago, before on-chip test compression was introduced, it was broadly believed that Logic BIST was going to be the next generation DFT methodology for manufacturing test. There were three main advantages of test compression over Logic BIST that contributed to its rapid adoption: simplicity of the design flow that does not require test points or x-bounding logic, excellent manageable and predictable test quality, and significant reduction of cost of test. Compression of volume of test data and test time by several orders of magnitude combined with on-chip PLLs controlling at-speed capture allow for dramatic reduction of cost of test. Disruptive technology of this magnitude has impact that goes far beyond cost of manufacturing test. Test compression has changed competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered not promising or not practical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnostics and yield learning are done in manufacturing environment. The presentation will discuss many of these issues, new opportunities, new and not so new challenges, as well as future technology roadmaps.
