DocumentCode
3017319
Title
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications
Author
Liveris, Nikolaos D. ; Zhou, Hai ; Banerjee, Prithviraj
Author_Institution
Northwestern Univ., Evanston, IL
fYear
2005
fDate
21-21 Dec. 2005
Firstpage
28
Lastpage
33
Abstract
In this paper, a new framework for formal verification is presented. The new framework called EVRM (efficient verification based on Mathematica) can be used for the property verification of a register transfer level implementation using a system level description as the golden model. EVRM is based on word level techniques and uses the Mathematica tool for the satisfiability procedure. Results show that it can be orders of magnitude faster than CBMC (Clarke et al., 2003) in proving property correctness or providing a counterexample for computation-intensive applications. For certain applications CBMC requires more than 5 hours to provide an answer, while EVRM provides an answer in less than 10 minutes
Keywords
computational complexity; formal verification; mathematics computing; Mathematica tool; RTL verification framework; formal verification; register transfer level; system level description; Automata; Boolean functions; Circuit simulation; Computer applications; Data structures; Digital integrated circuits; Encoding; Formal verification; Logic; Mathematical model;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2005. Proceedings. 14th Asian
Conference_Location
Calcutta
ISSN
1081-7735
Print_ISBN
0-7695-2481-8
Type
conf
DOI
10.1109/ATS.2005.24
Filename
1575402
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