DocumentCode :
3017387
Title :
Repeater block planning under simultaneous delay and transition time constraints
Author :
Sarkar, Probir ; Koh, Cheng-Kok
Author_Institution :
Conexant Syst., Newport Beach, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
540
Lastpage :
544
Abstract :
We present a solution to the problem of repeater block planning under both delay and signal transition time constraints for a given floorplan. Previous approaches have considered only meeting the target delay of a net. However it has been observed that the repeater planning for meeting the delay target can cause signals on long interconnects to have very slow transition rates. Experimental results show that our new approach satisfies both timing constraints for an average of 79% of all global nets for six MCNC benchmark floorplans studied (at 1 GHz frequency), compared with an average of 22% for the repeater block planner reported previously
Keywords :
VLSI; circuit layout CAD; delays; integrated circuit interconnections; integrated circuit layout; timing; 1 GHz; IC layout; delay constraints; floorplan; interconnects; repeater block planning; signal transition time constraints; simultaneous delay/transition time constraints; Delay effects; Frequency; Meeting planning; Power system interconnection; Power system reliability; Repeaters; Signal design; Time factors; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
ISSN :
1530-1591
Print_ISBN :
0-7695-0993-2
Type :
conf
DOI :
10.1109/DATE.2001.915076
Filename :
915076
Link To Document :
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