DocumentCode
3017420
Title
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test
Author
Quan, Shaolei ; Qiang, Qiang ; Wey, Chin-Long
Author_Institution
Michigan State University, US
fYear
2005
fDate
18-21 Dec. 2005
Firstpage
70
Lastpage
75
Abstract
Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.
Keywords
CMOS technology; Circuit simulation; Circuit testing; Integrated circuit testing; Logic testing; Operational amplifiers; Stress; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2005. Proceedings. 14th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2481-8
Type
conf
DOI
10.1109/ATS.2005.49
Filename
1575409
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