Title :
A 0.8V 6.4µW compact mixed-signal front-end for neural implants
Author :
El-Kholy, Ahmed ; Ghoneima, Maged ; Sharaf, Khaled
Author_Institution :
Dept. of Electron. & Commun. Eng., Ain-Shams Univ., Cairo, Egypt
Abstract :
In this paper, a compact, reconfigurable, low-power mixed-signal neural front-end is presented. It employs a multi-bit ΣΔ DAC and a flexible digital filter in the feedback to suppress electrode DC offset up to ±50 mV. A low noise neural amplifier is used to amplify both spikes and local field potentials (LFPs). A second order gm-C anti-aliasing filter is used to filter out ΣΔ DAC quantization noise. A 8b 200 kS/s SAR ADC is proposed with 48.7 SNDR and 22.5 fJ/conv. step. The whole neural front-end achieves a low input-referred noise of 5.2 μVrms for a signal bandwidth of 10 kHz using a compact and highly programmable architecture. It consumes 6.4 μW from 0.8 V supply while occupying 0.049 mm2 in 0.13 μm CMOS.
Keywords :
CMOS digital integrated circuits; brain-computer interfaces; digital filters; digital-analogue conversion; low noise amplifiers; low-power electronics; prosthetics; sigma-delta modulation; ΣΔ DAC quantization noise; CMOS technology; SAR ADC; bandwidth 10 kHz; compact mixed-signal front-end; flexible digital filter; input-referred noise; local field potentials; low-noise neural amplifier; multibit ΣΔ DAC; neural implants; power 6.4 muW; reconfigurable low-power mixed-signal neural front-end; second-order gm-C antialiasing filter; size 0.13 mum; voltage 0.8 V; Band pass filters; Frequency modulation; Lead; Switches; Time domain analysis; Neural recording; antialiasing; brain machine interface; instrumentation amplifiers; neural interface;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271733
