VHDL-A: analog extension to VHDL

VHDL is an IEEE standardized language for the description and simulation of digital circuits and systems. Originally developed in the early 1980s, VHDL has achieved great success in electronic design automation, and is emerging as an indispensable tool to deal with complex ASIC system design. However, VHDL is primarily designed to model digital behavior. Nowadays, a majority of ASIC designs contain both analog and digital elements. Also, ultra-fast digital designs are composed of cells and interconnects that exhibit primarily analog character. Full system verification of an ASIC design needs modeling of its application environments, which are usually non-electrical such as mechanical and thermal. This paper describes VHDL-A: an IEEE effort towards a standardized analog extension of VHDL to address these needs. The emphasis of this paper is on main language concepts and features and how they can be used to describe and simulate mixed analog and digital designs