• DocumentCode
    3017977
  • Title

    Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks

  • Author

    Ding, Z. ; Hoare, R. ; Jones, A. ; Li, D. ; Shao, S. ; Tung, S. ; Zheng, J. ; Melhem, R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Pittsburgh Univ., PA, USA
  • fYear
    2005
  • fDate
    04-08 April 2005
  • Abstract
    Predictive multiplexed switching is a new approach for building interconnection switches for high performance parallel systems. This approach advocates sacrificing some link bandwidth in return for more efficient network control and simpler connection management. The main idea is to depart from the traditional packet and wormhole switching in favor of row data communication over established communication pipes (connections). The overhead of this circuit switching approach can be justified when established connections are repeatedly used before they are torn down. For this, we use multiplexing to allow multiple connections to share the same resources (links and switches), thus avoiding tearing down connections prematurely. The connection establishment overhead is further reduced by exploring communication locality and predictability in applications that exhibit these properties. We present the design of an interconnection system which is based on multiplexed switching and which establishes connections either reactively, in response to dynamically generated requests, or proactively, in response to compiler or application directives. A communication prediction component may be supported to reduce the network control overhead in applications that exhibit communication locality and predictability. The design is evaluated using hardware design, synthesis, and cycle-accurate simulation. Comparison with more traditional switching paradigms shows the potential of our predictive multiplexed switching approach.
  • Keywords
    circuit switching; multiprocessor interconnection networks; network routing; packet switching; parallel processing; program compilers; circuit switching; data communication; hardware design; high performance parallel systems; interconnection switches; multiprocessor networks; packet switching; predictive multiplexed switching; wormhole switching; Bandwidth; Buildings; Communication switching; Communication system control; Data communication; Hardware; Integrated circuit interconnections; Packet switching; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
  • Print_ISBN
    0-7695-2312-9
  • Type

    conf

  • DOI
    10.1109/IPDPS.2005.416
  • Filename
    1419926