• DocumentCode
    3018080
  • Title

    Enhancing Fault Simulation Performance by Dynamic Fault Clustering

  • Author

    Mirkhani, Shahrzad ; Navabi, Zainalabedin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Tehran Univ.
  • fYear
    2005
  • fDate
    21-21 Dec. 2005
  • Firstpage
    278
  • Lastpage
    283
  • Abstract
    Fault simulation algorithms used for large designs propagate a list of faults instead of a single fault in each simulation. Concurrent (Ulrich and Baker, 1974) and deductive (Armstrong, 1972) fault simulation algorithms are two examples of this kind of algorithm. In this paper, we utilize an optimization concept, which can be added to fault list propagating algorithms. In this concept, faults can be grouped into several disjoint fault sets. All faults in a group affect every line of the circuit in a similar way. Fault clustering is performed dynamically, based on a particular test vector, during the fault simulation process. This method causes less memory fragmentation, since there are a limited number of fault groups in each simulation time. On the other hand, it reduces faulty circuit calculation in fault simulation process compared with the traditional fault simulation methods. In addition, the generality of this concept makes it useful for behavioral fault simulation methods as well as traditional gate-level ones. We have implemented this method in the VHDL environment and tested it on ISCAS´85 benchmarks. Experimental results show that in large circuits the performance is at least doubled by this technique
  • Keywords
    automatic test pattern generation; fault simulation; hardware description languages; integrated circuit testing; VHDL; concurrent fault simulation algorithms; deductive fault simulation algorithms; dynamic fault clustering; fault list propagating algorithms; memory fragmentation; Algorithm design and analysis; Circuit faults; Circuit simulation; Circuit testing; Clustering algorithms; Computational modeling; Computer simulation; Design engineering; Fault detection; Integrated circuit testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • Conference_Location
    Calcutta
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.58
  • Filename
    1575442