Simple yet effective replication for FPGA partitioning

This paper deals with the partitioning of large digital designs for multiple FPGA based implementation. Partitioning for FPGAs is very constrained problem due to severe pin limitations. The approach described here uses efficient heuristics for replicating logic blocks. It is shown through experimentation that utilization can greatly be improved by replicating very small number of logic blocks. In addition, the effect of replication on fanout, board level design, and performance is also studied. It is found that replication of logic blocks using our approach does not lead to excessive load due to increased fanout. In some cases, replication of input/output blocks can result in enhanced utilization. The tool has been integrated with XILINX APR tools. Thus feasibility is established not by counting the logic blocks and I/O pins but by actually being able to place and route a given circuit