DocumentCode
3018141
Title
Verification of a microprocessor using real world applications
Author
Chang, You-Sung ; Lee, Seungjong ; Park, In-Cheol ; Kyung, Chong-Min
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fYear
1999
fDate
1999
Firstpage
181
Lastpage
184
Abstract
In this paper, we describe a fast and convenient verification methodology for microprocessor using large-size, real application programs as test vectors. The verification environment is based on automatic consistency checking between the golden behavioral reference model and the target HDL model, which are run in an handshaking fashion. In conjunction with the automatic comparison facility, a new HDL saver is proposed to accelerate the verification process. The proposed saver allows “restart” from the nearest checkpoint before the point of inconsistency detection regardless of whether any modification on the source code is made or not. It is to be contrasted with the conventional saver that does not allow restart when some design change, or debugging is made. We have proved the effectiveness of the environment through applying it to a real world example, i.e., Pentium-compatible processor design process. It was shown that the HDL verification with the proposed saver can be faster and more flexible than the hardware emulation approach. In short, it was demonstrated that restartability with source code modification capability is very important in obtaining the short debugging turnaround time by eliminating a large number of redundant simulations
Keywords
computer debugging; computer testing; digital simulation; fault diagnosis; formal verification; integrated circuit testing; microprocessor chips; HDL saver; HDL-based verification methodology; Pentium-compatible processor design process; automatic comparison facility; automatic consistency checking; debugging turnaround time; golden behavioral reference model; microprocessor verification; real application programs; restartability; source code modification capability; target HDL model; test vectors; verification environment; Acceleration; Application software; Circuit simulation; Debugging; Emulation; Hardware design languages; Microprocessors; Permission; Process design; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location
New Orleans, LA
Print_ISBN
1-58113-092-9
Type
conf
DOI
10.1109/DAC.1999.781306
Filename
781306
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