Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency

The generation, qualification and validation of structural patterns for transition and path delay faults present several problems due to various design, tools and tester constraints. This paper proposes a flow for the generation and selection of a reduced set of structural patterns for at-speed testing, based on pattern reuse across different fault models, and based on metrics of minimum single detect and a qualified N-detect coverage. Patterns generated using ATPG and deterministic BIST techniques are considered for large representative SOC designs. It is shown that significant reduction of up to 35% in the pattern volume is achieved without compromising the test quality. These pattern selection techniques are being deployed in different designs in Texas Instruments (India).