Automatic generation of hardware design properties from simulation traces

This paper studies the problem of automatic assertion extraction from simulation traces. Previous approaches to the assertion generation problem have focused on a single aspect of automatic assertion extractions, and have yielded often unfavorable results. We propose a framework that combines searching for known assertion via templates with frequent and sequential patterns mining, while constraining the search by some knowledge about the design. These constraints can be automatically extracted using static analysis methods from the Register Transfer Level (RTL) description of the design, or as a user input to the assertion detector. Our experimental results show that this approach helps in the detection of assertion patterns that are typically common and widely used in today´s RTL designs.