Modelling SoC devices for virtual test using VHDL

Virtual Test (VT) is a new technique to cut the time-to-marker especially for SoC products that inherently contain complex mixed-signal blocks. VT allows debugging test programs in a simulation environment if a fast and sufficiently accurate IC model can be made available. VHDL behavioural models turned out to be a very promising approach to cover both the needs of designers for the sign-off simulation on chip level and of test engineers for VT. The trade-offs between modelling effort, simulation performance and accuracy of results are discussed for VT applications based on an industrial example