Title :
Performance-driven integration of retiming and resynthesis
Author_Institution :
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
We present a novel approach to performance optimization by integrating retiming and resynthesis. The approach is oblivious of register boundaries during resynthesis. In addition, it guides resynthesis by a criterion that is directly tied to the performance target. The proposed approach obtains provable results. Experimental results further demonstrate the effectiveness of our approach
Keywords :
circuit CAD; circuit optimisation; logic CAD; sequential circuits; timing; CAD; performance optimization; performance-driven integration; resynthesis; retiming; timing optimisation; Circuit synthesis; Combinational circuits; Delay; Logic circuits; Optimization; Permission; Registers; Sequential circuits; Signal synthesis; Timing;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781319
