DocumentCode
3018347
Title
Performance-driven integration of retiming and resynthesis
Author
Pan, Peichen
Author_Institution
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
fYear
1999
fDate
1999
Firstpage
243
Lastpage
246
Abstract
We present a novel approach to performance optimization by integrating retiming and resynthesis. The approach is oblivious of register boundaries during resynthesis. In addition, it guides resynthesis by a criterion that is directly tied to the performance target. The proposed approach obtains provable results. Experimental results further demonstrate the effectiveness of our approach
Keywords
circuit CAD; circuit optimisation; logic CAD; sequential circuits; timing; CAD; performance optimization; performance-driven integration; resynthesis; retiming; timing optimisation; Circuit synthesis; Combinational circuits; Delay; Logic circuits; Optimization; Permission; Registers; Sequential circuits; Signal synthesis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location
New Orleans, LA
Print_ISBN
1-58113-092-9
Type
conf
DOI
10.1109/DAC.1999.781319
Filename
781319
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