Module placement for analog layout using the sequence-pair representation

This paper addresses the problem of device-level placement for analog layout. Different from most of the existing approaches employing basically simulated annealing optimization algorithms operating on flat Gellat-Jepsen spatial representations, we use a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we explain how specific features essential to analog placement, such as the ability to deal with symmetry and device matching constraints, can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment