DocumentCode
3018534
Title
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space
Author
Nicolici, Nicola ; Al-Hashimi, Bashir M.
Author_Institution
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
fYear
2001
fDate
2001
Firstpage
802
Abstract
Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation
Keywords
built-in self test; design for testability; discrete cosine transforms; high level synthesis; logic testing; BIST RTL data paths; area overhead; power dissipation; reliability; test application time; testability trade-offs; three dimensional design space; yield; Application software; Automatic testing; Built-in self-test; Computer aided software engineering; Discrete cosine transforms; Power dissipation; Power engineering computing; Space technology; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location
Munich
ISSN
1530-1591
Print_ISBN
0-7695-0993-2
Type
conf
DOI
10.1109/DATE.2001.915128
Filename
915128
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