• DocumentCode
    3018567
  • Title

    Coverage estimation for symbolic model checking

  • Author

    Hoskote, Yatin ; Kam, Timothy ; Ho, Pei-Hsin ; Zhao, Xudong

  • Author_Institution
    Strategic CAD Labs., Intel Corp., USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    300
  • Lastpage
    305
  • Abstract
    Although model checking is an exhaustive formal verification method, a bug can still escape detection if the erroneous behavior does not violate any verified property. We propose a coverage metric to estimate the “completeness” of a set of properties verified by model checking. A symbolic algorithm is presented to compute this metric for a subset of the CTL property specification language. It has the same order of computational complexity as a model checking algorithm. Our coverage estimator has been applied in the course of some real-world model checking projects. We uncovered several coverage holes including one that eventually led to the discovery of a bug that escaped the initial model checking effort
  • Keywords
    formal verification; specification languages; symbol manipulation; CTL property specification language; computational complexity; coverage estimation; formal verification; model checking; symbolic algorithm; Circuit simulation; Computational complexity; Design automation; Engines; Formal verification; Hardware design languages; Logic circuits; Permission; Specification languages; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1999. Proceedings. 36th
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-58113-092-9
  • Type

    conf

  • DOI
    10.1109/DAC.1999.781330
  • Filename
    781330