High-performance routing for field-programmable gate arrays

The advantages of field-programmable gate arrays (FPGAs) are sometimes eclipsed by a substantial performance penalty due to signal delay through the programmable routing resources. We propose a new FPGA routing construction that directly minimizes source-sink signal propagation delay based on a graph generalization of rectilinear Steiner arborescences (i.e. shortest-paths trees with minimum wirelength). Experimental results indicate that our new heuristic significantly reduces maximum source-to-sink pathlengths while using wirelength competitive with that of Steiner routing