Technology mapping for FPGAs with nonuniform pin delays and fast interconnections

Author

Gong, Jianya ; Yean-Yow Kwang ; Xu, Songjie

Author_Institution

Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

fYear

1999

fDate

1999

Firstpage

373

Lastpage

378

Abstract

In this paper we study the technology mapping problem for FPGAs with nonuniform pin delays and fast interconnections. We develop the PinMap algorithm to compute the delay optimal mapping solution for FPGAs with nonuniform pin delays in polynomial time based on the efficient cut enumeration. Compared with FlowMap without considering the nonuniform pin delays, PinMap is able to reduce the circuit delay by 15% without any area penalty. For mapping with fast interconnections, we present two algorithms, an iterative refinement based algorithm, named ChainMap, and a Boolean matching based algorithm, named HeteroBM, which combines Boolean matching techniques and a heterogeneous technology mapping mechanism. It is shown that both ChainMap and HeteroBM are able to significantly reduce the circuit delay by making efficient use of the FPGA fast interconnections resources

Keywords

Boolean algebra; delays; field programmable gate arrays; integrated circuit interconnections; iterative methods; logic CAD; Boolean matching; ChainMap algorithm; FPGA; HeteroBM algorithm; PinMap algorithm; circuit delay; fast interconnection; heterogeneous technology mapping; iterative refinement; logic synthesis; nonuniform pin delay; polynomial time; technology mapping; Computer science; Delay effects; Feedback; Field programmable gate arrays; Integrated circuit interconnections; Iterative algorithms; Minimization methods; Permission; Polynomials; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.781344

Filename

781344