• DocumentCode
    3018813
  • Title

    Thermal analysis of power cycling effects on high power IGBT modules by the boundary element method

  • Author

    Khatir, Zoubir ; Lefebvre, Stephane

  • Author_Institution
    INRETS, Arcueil, France
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    27
  • Lastpage
    34
  • Abstract
    The technology of high power IGBT modules has been significantly improved in the last few years against thermal fatigue. The most frequently observed failure mode, due to thermal fatigue, is solder cracks between the copper base plate and the DCB (direct copper bonding) substrate. Specific simulation tools are needed to carry out reliability research and to develop device lifetime models. In other respects, accurate temperature and flux distributions are essential when computing thermomechanical stresses in order to assess the lifetime of high power modules in real operating conditions. This study presents an analysis method based on the boundary element method (BEM) to investigate thermal behavior of high power semiconductor packages submitted to power cycling constraints. The paper describes the boundary integral equation which has been solved using the BEM and applied to the case of a high power IGBT module package (3.3 kV-1.2 kA). A validation of the numerical tool is presented by comparison with experimental measurements. Finally, the paper shows the effect of the IGBT silicon chip position on the DCB substrate on the thermal constraints. In particular, a slight shifting of the silicon chips may be sufficient to delay significantly the initiation and propagation of the cracks, allowing a higher device lifetime for the module
  • Keywords
    boundary integral equations; boundary-elements methods; insulated gate bipolar transistors; power bipolar transistors; semiconductor device measurement; semiconductor device models; semiconductor device packaging; semiconductor device reliability; soldering; thermal analysis; thermal stress cracking; 1.2 kA; 3.3 kV; Cu; DCB substrate; IGBT silicon chip position; Si; boundary element method; boundary integral equation; copper base plate; crack initiation; crack propagation; device lifetime; device lifetime models; direct copper bonding substrate; failure mode; measurements; numerical tool validation; operating conditions; power IGBT module package; power IGBT modules; power cycling constraints; power cycling effects; power modules; power semiconductor packages; reliability; simulation tools; solder cracks; temperature distributions; thermal analysis; thermal behavior; thermal fatigue; thermal flux distributions; thermomechanical stresses; Bonding; Computational modeling; Copper; Distributed computing; Fatigue; Insulated gate bipolar transistors; Semiconductor device packaging; Silicon; Substrates; Temperature distribution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Thermal Measurement and Management, 2001. Seventeenth Annual IEEE Symposium
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7803-6649-2
  • Type

    conf

  • DOI
    10.1109/STHERM.2001.915141
  • Filename
    915141