• DocumentCode
    3018830
  • Title

    Limitation of structural scan delay test

  • Author

    Mak, T.M.

  • Author_Institution
    Intel Corporation
  • fYear
    2005
  • fDate
    18-21 Dec. 2005
  • Firstpage
    471
  • Lastpage
    471
  • Abstract
    Beyond the traditional stuck-at fault model, there are transition fault model and path delay model, followed by many, many other fault models that have appeared over the years. Transition model essentially define a node that is slow to rise or slow to fall and that this slow transition make its way to a primary output. Meanwhile path delay fault is more precise and define that a slow event be propagated along specific paths to a particular primary output. Due to their name (transition/delay) and nature, these fault models would appear to detect structural delay faults (whether it is process induced or delay defect induced). There is a general belief in the industry that achieving good coverage with these models would guarantee high product quality.
  • Keywords
    Automatic test pattern generation; Clocks; Fault detection; Instruments; Lithography; Power system interconnection; Process design; Propagation delay; Signal design; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.74
  • Filename
    1575487