Title :
A pseudo relay-insensitive timing model to synthesising low-power asynchronous circuits
Author :
Garnica, O. ; Lanchares, Juan ; Hermida, Roman
Author_Institution :
Dept. Arquitectura de Comput., Univ. Complutense de Madrid, Spain
Abstract :
The aim of this paper is to present a new approach to creating high performance, low-power and low-area asynchronous circuits using high level design tools. In order to achieve this, we introduce the new timing model on which this approach is based on. Following this, we present the results from comparing, for a set of benchmarks, our implementation with other implementations
Keywords :
asynchronous circuits; logic design; performance evaluation; power consumption; timing; high level design tools; low-area asynchronous circuits; low-power asynchronous circuits; pseudo relay-insensitive timing model; timing model; Asynchronous circuits; Circuit synthesis; Delay; High performance computing; Logic circuits; Logic gates; Protocols; Timing; Upper bound; Wires;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.915146
