Title :
A design assembly framework for FPGA back-end acceleration
Author :
Frangieh, T. ; Athanas, Peter
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech Configurable Comput. Lab., Blacksburg, VA, USA
Abstract :
Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict FPGA adaptation in modern computing platforms. This work presents an FPGA development paradigm as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, qFlow, is implemented. Experiments show up to 7x speed-ups using the proposed paradigm compared to the vendor tool flows.
Keywords :
field programmable gate arrays; logic partitioning; network routing; FPGA adaptation; FPGA back-end acceleration; FPGA development paradigm; FPGA productivity; computing platforms; design assembly framework; logic partitioning; logic placement; logic routing; qFlow; vendor tool; Acceleration; Assembly; Field programmable gate arrays; Hardware; Productivity; Routing; Table lookup; Back-End Acceleration; FPGA; Modular-Assembly; Productivity;
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4673-2919-4
DOI :
10.1109/ReConFig.2012.6416718
