A design assembly framework for FPGA back-end acceleration

Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict FPGA adaptation in modern computing platforms. This work presents an FPGA development paradigm as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, qFlow, is implemented. Experiments show up to 7x speed-ups using the proposed paradigm compared to the vendor tool flows.