Title :
Gradient-based optimization of custom circuits using a static-timing formulation
Author :
Conn, A.R. ; Elfadel, I.M. ; Molzen, W.W., Jr. ; O´Brien, P.R. ; Strenski, P.N. ; Visweswariah, C. ; Whan, C.B.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper describes a method of optimally sizing digital circuits on a static-timing basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradient-based, nonlinear optimization and can accommodate transistor-level schematics without the need for pre-characterization. It employs efficient time-domain simulation and gradient computation for each channel-connected component. A large-scale, general-purpose, nonlinear optimization package is used to solve the tuning problem. A prototype tuner has been developed that accommodates combinational circuits consisting of parameterized library cells. Numerical results are presented
Keywords :
application specific integrated circuits; circuit optimisation; circuit tuning; combinational circuits; gradient methods; logic design; logic simulation; timing; channel-connected component; combinational circuits; custom circuits; digital circuits; gradient computation; gradient-based nonlinear optimization; gradient-based optimization; large-scale general-purpose package; numerical results; optimal sizing; parameterized library cells; static-timing formulation; time-domain simulation; transistor-level schematics; tuning problem; Circuit optimization; Circuit simulation; Computational modeling; Digital circuits; Large-scale systems; Logic; Optimization methods; Packaging; Prototypes; Time domain analysis;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781359
