A versatile UDP/IP based PC ↔ FPGA communication platform

We present a substantially improved version of our popular UDP/IP core for simple and fast PC ↔ FPGA communication over Gigabit Ethernet. We provide a novel feature to automatically configure (previously hard-coded) internal settings on the FPGA. Thereby, we substantially reduce the installation overhead when a FPGA shall communicate with several different PCs. The UDP/IP core is designed to occupy a minimum amount of hardware resources on the FPGA. On the PC side, this new automatic configuration protocol can be used and invoked via a C software interface which provides convenient functions for setting up the connection to the FPGA device and sending/retrieving arrays of common C data types to/from the UDP/IP core on the FPGA. The initial UDP/IP core version is available under the LGPL license at http://opencores.org/project, udp_ip__core while the improved version of the core, including the C software interface (also under LGPL), is available at http://opencores.org/project, pc_fpga_com.