Title :
Improved delay prediction for on-chip buses [high-level synthesis]
Author :
Pomerleau, Real G. ; Franzon, Paul D. ; Bilbro, Griff L.
Author_Institution :
North Carolina State Univ., Raleigh, NC, USA
Abstract :
In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its ports. In addition, we propose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation in floorplanners during behavioral synthesis
Keywords :
calibration; circuit layout CAD; high level synthesis; integrated circuit layout; wiring; Elmore delay; behavioral synthesis; bi-directional buses; calibration procedure; delay prediction; floorplanners; high-level synthesis; on-chip buses; wiring delay; Bidirectional control; Calibration; Delay; High level synthesis; Job shop scheduling; Partitioning algorithms; Permission; Topology; Very large scale integration; Wiring;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781366
