• DocumentCode
    3019304
  • Title

    Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

  • Author

    Wu, Hsiang-Huang ; Shen, Chung-Ching ; Bhattacharyya, Shuvra S. ; Compton, Katherine ; Schulte, Michael ; Wolf, Marilyn ; Zhang, Tong

  • Author_Institution
    Univ. of Maryland, College Park, MD, USA
  • fYear
    2010
  • fDate
    7-10 Nov. 2010
  • Firstpage
    2121
  • Lastpage
    2125
  • Abstract
    Processing structures based on arrays of computational elements form an important class of architectures, which includes field programmable gate arrays (FPGAs), systolic arrays, and various forms of multicore processors. A wide variety of design methods and tools have been targeted to regular processing arrays involving homogeneous processing elements. In this paper, we introduce the concept of field programmable X arrays (FPXAs) as an abstract model for design and implementation of heterogeneous multiprocessor arrays for signal processing systems. FPXAs are abstract structures that can be targeted for implementation on application-specific integrated circuits, FPGAs, or other kinds of reconfigurable processors. FPXAs can also be mapped onto multicore processors for flexible emulation. We discuss the use of dataflow models as an integrated application representation and intermediate representation for efficient specification and mapping of signal processing systems on FPXAs. We demonstrate our proposed models and techniques with a case study involving the embedding of an application-specific FPXA system on an off-the-shelf FPGA device.
  • Keywords
    application specific integrated circuits; field programmable gate arrays; logic design; microprocessor chips; reconfigurable architectures; signal processing; systolic arrays; FPGA; FPXA; application-specific integrated circuits; computational elements; field programmable X arrays; field programmable gate arrays; multicore processors; multiprocessor arrays; real-time signal processing; reconfigurable processors; signal processing systems; systolic arrays; Computer architecture; Decoding; Field programmable gate arrays; Integrated circuit modeling; Routing; Signal processing; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    978-1-4244-9722-5
  • Type

    conf

  • DOI
    10.1109/ACSSC.2010.5757924
  • Filename
    5757924