CMOS sizing rule for high performance long interconnects

During the past fifteen years, the role of interconnects has turned to be the determining factor of the overall performance of VLSI circuits. In this work, the authors present a new transistor sizing rule for long interconnect buffers. It is shown how transmission line properties of long interconnects alter the behaviour of the CMOS buffer, forcing transistors to work mainly in linear mode rather than in saturation as is usually assumed. This unusual condition leads to strong mismatching between predicted and actual driver output impedance if conventional sizing rules are used. The proposed sizing rule allows true line matching to be achieved thus either minimizing delay or preserving signal integrity